Interface state density engineering in Hf1-xZrxO2/SiON/Si gate stack

This work investigates the interface state density, Dit by conductance method for two different processing conditions: (1) cyclic deposition and slot-plane-antenna (SPA) Ar plasma exposure, DSDS, and (2) cyclic deposition and annealing, DADA, during the deposition of ALD Hf1-xZrxO2 to fabricate the TiN/Hf1-xZrxO2/SiON/Si gate stack. The Zr percentage was varied in the dielectrics from x = 0 to 0.31 and 0.8 for DSDS processing and x = 0 to 0.8 for DADA processing. The control samples were deposited with standard atomic layer deposition (ALD) process (As-Dep) without any cyclic treatment. The addition of ZrO2 and SPA plasma exposure is found to suppress interface state generation. DSDS Hf1-xZrxO2 with x = 0.8 demonstrated superior equivalent oxide thickness downscaling and the lowest Dit. The electron affinity variation of Hf and Zr ion seems to contribute to reduced Dit generation after a constant voltage stress. On the other hand, DADA process increases the midgap Dit when Zr is added to HfO2. In addition, DADA processed dielectrics showed higher degradation when stressed because of increased trap assisted tunneling through charged grain boundaries. Furthermore, DSDS Hf1-xZrxO2 (x = 0.8) with two different interfacial layers: (1) UV nitridation of chemically grown SiO2 and (2) plasma oxynitride grown after removing the chemically grown SiO2 was investigated. The interface characteristics observed for SiON formed by UV nitridation seems to be better as compared to that formed by plasma oxynitride, which is attributed to the more uniform nitrogen incorporation by UV nitridation. (C) 2015 American Vacuum Society.