A Novel Directory Based Hybrid Cache Coherence Protocol for Shared Memory Multiprocessors

While addressing cache coherency in shared memory multiprocessors, traditional snoopy based pure write update (PWU) and pure write invalidate (PWI) protocols have many issues including low bandwidth, high memory latency, and large cache miss ratio. This paper presents a directory based hybrid cache coherence protocol to better address the cache coherency and improve performance of shared memory multiprocessors. The requests to be processed are selected by using the proposed directory scheme and considering priority through non-starving mode to facilitate small sharer groups with a reasonable waiting time. Different read and write requests on 8-, 16-, and 32-core multiprocessors are considered. Experimental results show that the proposed strategy decreases bandwidth requirement about 37% than the PWU strategy. The results also indicate that the proposed strategy decreases memory latency by up to 12% and cache miss ratio by up to 22% when compared with those of the PWI strategy.