A study on lower saturation voltage of dual-gate thin-film a-IGZO MOS transistors

被引：1

作者：

Agarwal, Tarun Kumar ^{[1
]}

Siskos, Aris ^{[1
]}

De Roose, Florian ^{[1
]}

Dehaene, Wim ^{[1
,2
]}

Myny, Kris ^{[1
]}

Papadopoulos, Nikolas ^{[1
]}

机构：

[1] IMEC, TFDS, Leuven, Belgium

[2] KULeuven, ESAT, Leuven, Belgium

来源：

PROCEEDINGS OF THE 2021 IEEE INTERNATIONAL CONFERENCE ON FLEXIBLE AND PRINTABLE SENSORS AND SYSTEMS (FLEPS) | 2021年

基金：

欧洲研究理事会;

关键词：

amorphous indium-gallium-zinc oxide (a-IGZO); thin-film transistor (TFT); frontgate (FG); backgate (BG); metal-oxide-semiconductor (MOS);

D O I：

10.1109/FLEPS51544.2021.9469847

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This work focuses on an amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin-film transistor (TFT) model with lower saturation voltage for dual-gate (DG) TFTs compared to single-gate (SG) TFTs. The addition of a backgate in dual-gate TFTs saturates the drain current at one half of the V-DS required for SG devices when front and backgate oxides are matched. This behaviour can be expected for various configurations of DG TFTs. TFTs with gate and backgate shorted, with gate or backgate connected to source, and in diode load are discussed. The derived drain current equation for DG devices explains the lower saturation voltage and allows V-DS,V-Sat extraction. The model has been verified by characterizing different configurations, and comparing them to the device model simulations.

引用

页数：4

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