Rule-based Equivalence Checking of System-level Design Descriptions

被引：1

作者：

Yoshida, Hiroaki ^{[1
]}

Fujita, Masahiro ^{[1
]}

机构：

[1] Univ Tokyo, VLSI Design & Educ Ctr, Tokyo 1138654, Japan

来源：

2009 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLUMES I & II: COMMUNICATIONS, NETWORKS AND SIGNAL PROCESSING, VOL I/ELECTRONIC DEVICES, CIRUITS AND SYSTEMS, VOL II | 2009年

关键词：

D O I：

10.1109/ICCCAS.2009.5250314

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents our study on rule-based equivalence checking of system-level design descriptions. The rule-based equivalence checking proves the equivalence of two system-level design descriptions by applying equivalence rules in a bottom-up manner. In this paper, we first introduce our intermediate representation of system-level design, and then show a set of representative equivalence rules. Since our equivalence checking method is based on potential internal equivalences identified by using random simulation, we also present how to prove the equivalence based on such potential internal equivalences. Finally, we explain our implementation of the rule-based equivalence checker and demonstrate its feasibility and efficiency using an example design.

引用

页码：1139 / 1143

页数：5

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