RISA: A hardware platfonn for evolutionary design

被引：0
|
作者：
Greensted, Andrew J. [1 ]
Tyrrell, Andy M. [1 ]
机构：
[1] Univ York, Dept Elect, York YO10 5DD, N Yorkshire, England
来源：
2007 IEEE WORKSHOP ON EVOLVABLE AND ADAPTIVE HARDWARE | 2007年
基金：
英国工程与自然科学研究理事会;
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The Reconfigurable Integrated System Array is a new form of field programmable digital device incorporating both hardware and software reconfigurable elements. RISA was developed specifically for implementing biologically inspired electronic systems. The architecture is particularly suited for Investigating evolvable hardware due to the flexibility of RISA's configuration system. Fine grained partial reconfiguration is supported and random configuration bitstreams will not cause device damage. This paper describes the new RISA chip and the features that make it suitable for bio-inspired applications.
引用
收藏
页码：1 / +
页数：2
相关论文
共 50 条
  • [1] Evolutionary hardware design
    Sekanina, Lukas
    VLSI CIRCUITS AND SYSTEMS V, 2011, 8067
  • [2] Extrinsic evolvable hardware on the RISA architecture
    Greensted, A. J.
    Tyrrell, A. M.
    EVOLVABLE SYSTEMS: FROM BIOLOGY TO HARDWARE, PROCEEDINGS, 2007, 4684 : 244 - +
  • [3] A new variable topology for evolutionary hardware design
    Chen, Chih-Yung
    Hwang, Rey-Chue
    EXPERT SYSTEMS WITH APPLICATIONS, 2009, 36 (01) : 634 - 642
  • [4] Evolvable hardware - Using evolutionary computation to design and optimize hardware systems
    Lohn, Jason D.
    Hornby, Gregory S.
    IEEE COMPUTATIONAL INTELLIGENCE MAGAZINE, 2006, 1 (01) : 19 - 27
  • [5] A methodology for reconfigurable hardware design based upon evolutionary computation
    Fernández, F
    Hidalgo, JI
    Lanchares, J
    Sánchez, JM
    MICROPROCESSORS AND MICROSYSTEMS, 2004, 28 (07) : 363 - 371
  • [6] A novel single chip evolutionary hardware design using FPGAs
    Slorach, CG
    Sharman, KC
    CONFIGURABLE COMPUTING: TECHNOLOGY AND APPLICATIONS, 1998, 3526 : 114 - 123
  • [7] Hardware-in-the-Loop Simulation based Evolutionary Design of Image Filter
    Zhang, Kaifeng
    Lu, Huanzhang
    Xiao, Shanzhu
    Hu, Weidong
    ELEKTRONIKA IR ELEKTROTECHNIKA, 2014, 20 (07) : 61 - 64
  • [8] Parallelism of Evolutionary Design of Image Filters for Evolvable Hardware Using GPU
    Wu, Chih-Hung
    Chiang, Chin-Yuan
    Chen, Yi-Han
    2013 14TH ACIS INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING, ARTIFICIAL INTELLIGENCE, NETWORKING AND PARALLEL/DISTRIBUTED COMPUTING (SNPD 2013), 2013, : 592 - 597
  • [9] Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation
    Abe, M
    Arai, H
    Kawamata, M
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 528 - 531
  • [10] A Game-based Genetic Algorithm Approach for Evolutionary Hardware Design
    Xu Hai-qin
    Li Long-fei
    Ding Yong-sheng
    ICIEA: 2009 4TH IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS, VOLS 1-6, 2009, : 3737 - +
12345