OVERVIEW OF A FPGA-BASED OVERLAY PROCESSOR

This paper presents the overview of an overlay architecture on FPGA (OPU). It is applicable to general CNN acceleration with software like programmablility and fast compilation time. Good portability is guaranteed as only executable codes are reloaded for applicationswitch without FPGA re-synthesis. Our OPU instructions have complicated functions with variable runtimes but have a uniform length of 32 bits. This large granularity of instructions makes it easier to develop compiler and micro-architecture. Thus, OPU is a good candidate for domain specific processor without large volume. Experiments results show that OPU can achieve around 90 percent of runtime computing resource utilization (PE efficiency) among eight different network applications, which is 2% - 48% better compared with existing customized accelerators.