Novel FPGA-based pipelined floating point FFT processor

被引：0
|
作者：
Wei, Li [1 ]
Jun, Wang [1 ]
机构：
[1] Beijing Univ Aeronaut & Astronaut, Sch Elect & Informat Engn, Beijing 100083, Peoples R China
来源：
IEICE ELECTRONICS EXPRESS | 2010年 / 7卷 / 04期
关键词：
FFT; pipelined; floating point; FPGA;
D O I：
10.1587/elex.7.268
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Two novel architectures for pipelined floating point fast Fourier transform on FPGA are presented. The new radix-2(2) two-path delay feedback (R2(2)TDF) architecture leads to 50% area saving for floating point complex adders compared with the radix-2(2) single-path delay feedback (R2(2)SDF) architecture. Besides a new hybrid architecture is presented which mixes the R2(2)TDF and R2(2)TDF butterfly structures and is flexible and efficient for FPGA implementation.
引用
收藏
页码：268 / 272
页数：5
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