A 7GS/s Complete-DDFS-Solution in 65nm CMOS

被引：1

作者：

Alonso, Abdel Martinez ^{[1
]}

Miyahara, Masaya ^{[1
]}

Matsuzawa, Akira ^{[1
]}

机构：

[1] Tokyo Inst Technol, Dept Elect & Elect Engn, Tokyo 1528552, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2018年 / E101C卷 / 04期

关键词：

complete-DDFS-solution; high-speed DDFS; CMOS; RDAC; RSTC-DEM; rail-to-rail operation; two-times interleaved; DIRECT DIGITAL SYNTHESIZER; FREQUENCY-SYNTHESIZER; CLOCK FREQUENCY; DAC; BANDWIDTH;

D O I：

10.1587/transele.E101.C.206

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 7GS/s complete-DDFS-solution featuring a two-times interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for random swapping thermometer coding dynamic element matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The proposed techniques enable a 7 GS/s operation with a spurious-free dynamic range better than 32dBc over the full Nyquist bandwidth. The worst case narrowband SFDR is 42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s . 2((SFDR/6))/W. A proof-of-concept chip with an active area of only 0.22mm(2) was measured in prototypes encapsulated in a 144-pins low profile quad flat package.

引用

页码：206 / 217

页数：12

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