A 2nd-order Delta Sigma AD Modulator using Dynamic Amplifier and Dynamic SAR Quantizer

被引：0

作者：

Pan, Chunihui ^{[1
]}

San, Hao ^{[1
]}

Shibata, Tsugumichi ^{[1
]}

机构：

[1] Tokyo City Univ, Setagaya Ku, Tamazutsumi 1-28-1, Tokyo 1588557, Japan

来源：

2016 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS) | 2016年

关键词：

Multi-bit Delta Sigma modulator; Ring amplifier; Dynamic comparator;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A proof-of-concept Delta Sigma AD modulator using dynamic analog components is designed and fabricated in 90nm CMOS technology. The measurement results of an experimental prototype demonstrate the feasibility of the proposed switched-capacitor (SC) architecture to realize a 2nd-order Delta Sigma AD modulator with ring amplifier based integrators and dynamic comparator based successive approximation register (SAR) quantizer. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feedforward modulator is realized by a passive-adder embedded SAR analog-to-digital converter (ADC) which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power when a pre-amplifier is not used. Measurement results of peak SNDR=77.51dB and SNR=80.08dB are achieved while a sinusoid -1dBFS input is sampled at 12MS/s for the bandwidth is BW=94kHz. The total analog power consumption of the modulator is 0.37mW while the supply voltage is 1.1V.

引用

页码：528 / 532

页数：5

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