A serial-parallel architecture for two-dimensional discrete cosine and inverse discrete cosine transforms

被引：21
|
作者：
Lim, H
Piuri, V
Swartzlander, EE
机构：
[1] Lucent Technol, Cisco Syst, San Jose, CA 95134 USA
[2] Politecn Milan, Dept Elect & Informat, I-20133 Milan, Italy
[3] Univ Texas, Dept Elect & Comp Engn, Austin, TX 78712 USA
来源：
IEEE TRANSACTIONS ON COMPUTERS | 2000年 / 49卷 / 12期
关键词：
application specific processor architecture; Discrete Cosine Transform; Inverse Discrete Cosine Transform; image compression; serial-parallel processor; systolic array;
D O I：
10.1109/12.895848
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The Discrete Cosine and Inverse Discrete Cosine Transforms are widely used toots in many digital signal and image processing applications. The complexity of these algorithms often requires dedicated hardware support to satisfy the performance requirements of hard real-time applications. This paper presents the architecture of an efficient implementation of a two-dimensional DCT/IDCT transform processor via a serial-parallel systolic array that does not require transposition.
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页码：1297 / 1309
页数：13
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