Novel Approach to Design DPL-based Ternary Logic Circuits

被引：0
|
作者：
Singh, Narendra Deo [1 ]
Singh, Rakesh Kumar [1 ]
Raj, Rahul [1 ]
Jyoti, Shivam [1 ]
Saha, Aloke [1 ]
机构：
[1] Dr BC Roy Engn Coll, Dept Elect & Commun Engn, Durgapur, India
来源：
PROCEEDINGS OF 2018 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES KOLKATA CONFERENCE (IEEE EDKCON) | 2018年
关键词：
Double Pass-transistor Logic (DPL); hot-spot; Interconnect complexity; Ternary logic; Wave-pipelining;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Present paper introduces a novel strategy to design Double Pass-transistor Logic (DPL) based Ternary (base-3) logic circuit in favour of wave-pipelined applications. Ternary can be a feasible candidate to replace conventional binary (base-2) number system due to faster computation, reduced interconnect complexity, reduced fan-in/fan-out, less storage requirement and so on. Careful design with proper coarse and fine tuning of wave-pipelined circuit can improve the overall performance and reliability of digital SOC. DPL is a favourable candidate for wave-pipelining and is employed in this work. Ternary digit ("trit") value "0", "1" and "2" are coded with 0 V, 0.9 V and 1.8 V respectively. In order to validate proposed strategy the 2-input TXOR, TAND and TOR circuits are designed and the simulation results are verified. Speed-power performance of designed circuit is recorded. All the simulations are carried out on TSMC 0.18 mu m CMOS technology with 1.8 V supply rail and at 25 degrees C temperature using Tanner EDA.V13.
引用
收藏
页码：631 / 635
页数：5
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