Study on the Key Technology of Integrated Analog Chip Test and System Design

被引：0
|
作者：
Liu Jingmeng [1 ]
Liao Min [1 ]
Chen Weihai [1 ]
Xu Dong [2 ]
机构：
[1] Beijing Univ Aeronaut & Astronaut, Sch Automat, Beijing 100191, Peoples R China
[2] Beijing Univ Aeronaut & Astronaut, Robot Inst, Beijing 100191, Peoples R China
来源：
ICIEA: 2009 4TH IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS, VOLS 1-6 | 2009年
关键词：
integrated analog chip; AD converter; LCD; self-recovery fuse; bus; SIGNAL;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
An integrated analog chip tester has been designed. Since we need to test the analog voltage of analog devices, a kernel architecture based on Single Chip Computer(MCU) and AD converter has been designed. In order to solve the possible blight to tester caused by the damaged chips. This paper presents a technology for isolating inside and outside bus, a technology for double power supplies and a technology for power supply protection. The whole design idea of the tester is introduced in detail. AD converter circuit, DA converter circuit, Op amp testing circuit, CW3524 testing circuit and LCD interface circuit have been designed. The procedure of software design is presented, and the primary software modules are explained in detail. Experiment showpiece has been developed. The results of experiments verify the correctness of the design.
引用
收藏
页码：484 / +
页数：3
相关论文
共 50 条
  • [1] Key technologies of system on chip design
    ShaoJun Wei
    Science in China Series F: Information Sciences, 2008, 51 : 790 - 798
  • [2] Key technologies of system on chip design
    Wei ShaoJun
    SCIENCE IN CHINA SERIES F-INFORMATION SCIENCES, 2008, 51 (06): : 790 - 798
  • [3] Key technologies of system on chip design
    WEI ShaoJun Institute of Microelectronics
    Science in China(Series F:Information Sciences), 2008, (06) : 790 - 798
  • [4] VISION SYSTEM - A KEY TECHNOLOGY FOR CHIP ASSEMBLY
    SILBERRING, P
    SOLID STATE TECHNOLOGY, 1994, 37 (09) : 79 - 82
  • [5] Study of Key Technology for Automatic Test and Fault Diagnosis System
    Chen Jianhui
    Lian Guangyao
    Gao Fengqi
    Song Yingchen
    PROCEEDINGS OF THE SECOND INTERNATIONAL SYMPOSIUM ON TEST AUTOMATION & INSTRUMENTATION, VOL. 3, 2008, : 1650 - 1653
  • [6] An integrated system-on-chip test framework
    Larsson, E
    Peng, Z
    DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 138 - 144
  • [7] Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip
    Zhao, Dan
    Upadhyaya, Shambhu
    Margala, Martin
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (07) : 1411 - 1418
  • [8] Design and technology development of a bipolar array chip for analog ASICs
    Kal, S
    Das, S
    Pal, R
    Basu, PK
    Pillai, SV
    Lahiri, SK
    IETE TECHNICAL REVIEW, 1998, 15 (1-2) : 83 - 98
  • [9] Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications
    Deshpande, HV
    Cheng, BH
    Woo, JCS
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (09) : 1558 - 1565
  • [10] Analog Integrated Circuits Parameters Online Test System for Accelerated Test
    Huang, Jiaoying
    Cui, Can
    Gao, Cheng
    Lv, Xubo
    PROCEEDINGS OF 2016 11TH INTERNATIONAL CONFERENCE ON RELIABILITY, MAINTAINABILITY AND SAFETY (ICRMS'2016): INTEGRATING BIG DATA, IMPROVING RELIABILITY & SERVING PERSONALIZATION, 2016,
12345