Physics based model for potential distribution and threshold voltage of gate-all-around tunnel field effect transistor (GAA-TFET)

被引:2
|
作者
Usha, C. [1 ]
Vimala, P. [1 ]
Ramakrishnan, V. N. [2 ]
机构
[1] Dayananda Sagar Coll Engn, Dept Elect & Commun, Bangalore 560078, Karnataka, India
[2] Vellore Inst Technol, Dept Elect & Commun, Vellore 632014, Tamil Nadu, India
关键词
Tunnel field effect transistor; Surface potential; Threshold voltage; Threshold voltage roll off; Drain current; TCAD Simulation; FET; DESIGN;
D O I
10.1016/j.matpr.2020.10.946
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In this paper, we propose physics based modeling for p-type surrounding gate TFET with single material gate. The surface potential is modeled from 2-D Poisson's equation using Parabolic Approximation method. From the surface potential equation threshold voltage, threshold voltage roll off, drain current and Subthreshold Swing is modeled. The simulation of the model provides the threshold of 0.4 V, threshold voltage roll off less than 0.1 and Subthreshold Swing of 41 mV/dec. The model is validated using ATLAS TCAD Simulation Tool. (C) 2019 Elsevier Ltd. All rights reserved. Selection and Peer-review under responsibility of the scientific committee of the 2nd International Conference on Nanoscience and Nanotechnology.
引用
收藏
页码:4052 / 4057
页数:6
相关论文
共 50 条
  • [41] A Study on the Performance of Gate-All-Around Heterojunction Tunnel Field-Effect Transistors Based on Polarization Effect
    Guan, Yunhe
    Dou, Zhen
    Lu, Jiachen
    Sun, Weihan
    Wang, Shaoqing
    Liu, Xiangtai
    Chen, Haifeng
    ACS APPLIED ELECTRONIC MATERIALS, 2024, 6 (06) : 4635 - 4642
  • [42] Analytical Modeling of Threshold Voltage for Dual-Metal Double-Gate Gate-All-Around (DM-DG-GAA) MOSFET
    Ganapati, Reddi
    Samoju, Visweswara Rao
    Jammu, Bhaskara Rao
    SILICON, 2021, 13 (09) : 2869 - 2880
  • [43] Analytical Modeling of Threshold Voltage for Dual-Metal Double-Gate Gate-All-Around (DM-DG-GAA) MOSFET
    Reddi Ganapati
    Visweswara Rao Samoju
    Bhaskara Rao Jammu
    Silicon, 2021, 13 : 2869 - 2880
  • [44] Ge Condensation Process for High ON/OFF Ratio of SiGe Gate-All-Around Nanowire Tunnel Field-Effect Transistor
    Lee, Ryoongbin
    Lee, Junil
    Kim, Sangwan
    Lee, Kitae
    Kim, Sihyun
    Kim, Soyoun
    Choi, Yunho
    Park, Byung-Gook
    2019 SILICON NANOELECTRONICS WORKSHOP (SNW), 2019, : 51 - 52
  • [45] Analytical Threshold Voltage Model of Gate All Around Triple Metal Tunnel FET
    Bagga, Navjeet
    Dasgupta, S.
    2017 CONFERENCE ON EMERGING DEVICES AND SMART SYSTEMS (ICEDSS), 2017, : 146 - 149
  • [46] Peculiarities of the SCLC Effect in Gate-All-Around Silicon Nanowire Field-Effect Transistor Biosensors
    Zhang, Yongqiang
    Boichuk, Nazarii
    Pustovyi, Denys
    Chekubasheva, Valeriia
    Long, Hanlin
    Petrychuk, Mykhailo
    Vitusevich, Svetlana
    ADVANCED ELECTRONIC MATERIALS, 2024, 10 (07)
  • [47] Variability-Aware Simulation Strategy for Gate-All-Around Vertical Field Effect Transistor
    Ko, Kyul
    Kang, Myounggon
    Jeon, Jongwook
    Shin, Hyungcheol
    JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2019, 19 (10) : 6715 - 6721
  • [48] Study of line edge roughness on various types of gate-all-around field effect transistor
    Min, Jinhong
    Shin, Changhwan
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 35 (01)
  • [49] Failure Analysis of Gate-all-around Nanowire Field Effect Transistor Under TLP Test
    Zhang, Guoyan
    Dong, Aihua
    Liu, Nie
    Tian, Rui
    Yang, Xuejiao
    Liu, Zhiwei
    Lee, Kohui
    Lin, Horng-Chih
    Liou, Juin J.
    Wang Yuxin
    2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2014,
  • [50] Double-gate tunnel field-effect transistor: Gate threshold voltage modeling and extraction
    Li Yu-chen
    Zhang He-ming
    Hu Hui-yong
    Zhang Yu-ming
    Wang Bin
    Zhou Chun-yu
    JOURNAL OF CENTRAL SOUTH UNIVERSITY, 2014, 21 (02) : 587 - 592