Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications

被引：4
|
作者：
Deak, Norbert [1 ]
Cret, Octavian [2 ]
Hedesiu, Horia [3 ]
机构：
[1] Natl Instruments, Cluj Napoca Branch, Cluj Napoca, Romania
[2] Tech Univ Cluj Napoca, Dept Comp Sci, Cluj Napoca, Romania
[3] Tech Univ Cluj Napoca, Dept Elect Machines, Cluj Napoca, Romania
来源：
2019 27TH IEEE ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM) | 2019年
关键词：
D O I：
10.1109/FCCM.2019.00050
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper introduces an efficient automatic floorplanning algorithm, which takes into account the heterogeneous architectures of modern FPGA families, as well as partial reconfiguration (PR) constraints, introducing the aspect ratio (AR) constraint to optimize routing. The algorithm generates possible placements of the partial modules, and then applies a recursive pseudo-bipartitioning heuristic search to find the best floorplan. The experiments show that its performance is significantly better than the one of other algorithms in this field.
引用
收藏
页码：309 / 309
页数：1
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