Efficient hardware implementation for H.264/AVC motion estimation

被引：0

作者：

Bojnordi, Mahdi Nazm ^{[1
]}

Semsarzadeh, Mehdi ^{[1
]}

Hashemi, Mahmoud Reza ^{[1
]}

Fatemi, Omid ^{[1
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Nano Elect Ctr Excellence, Tehran, Iran

来源：

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS | 2006年

关键词：

H.264/AVC; VBSME; parallel architecture;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Variable block size motion estimation (VBSME) is adopted in H.264/AVC to improve the coding efficiency. However, supporting various block sizes significantly increases the complexity of both video encoding and decoding. In this paper a multi-level parallel architecture for H.264/AVC motion estimation is proposed. A SIMD architecture is proposed for absolute differentiator and accumulator (ADA). Using the ADA as the main processing engine, a cost and performance SAD processor is proposed. Experimental results indicate that more than 100% performance improvement is achieved by the proposed architectures compared to the state-of-the-art architectures with similar resources.

引用

页码：1749 / +

页数：2

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