IIP3 optimization through body biasing in Low Noise Amplifiers

This paper studies the effect of bulk control on the input third order intercept point (IIP3) of a CMOS Low Noise Amplifier (LNA) at RF frequencies. The circuit reveals an optimum bulk biasing at which a maximum IIP3 is achieved under low power consumption. The cascode LNA, here reported, operates at 2.4 GHz and is implemented in a 0.13 mu m CMOS process. Supplied under 1.1V, it achieves nominal 13.86 dB gain and 3.23 dB noise figure (NF) for a 3mA current consumption. Tuning the bulk to source voltage to -0.55 V the IIP3 exhibits a maximum 6.63 dBm for a 1.1 mW overall power consumption. Whereas the gain and NF reach 8.2 dB and 4.8 dB respectively.