Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2m) Using Double Parity Prediction Scheme

被引:5
|
作者
Lee, Chiou-Yng [1 ]
Chiou, Che Wun [2 ]
Lin, Jim-Min [3 ]
机构
[1] Lunghwa Univ Sci & Technol, Dept Comp Informat & Network Engn, Tao Yuan 333, Taiwan
[2] Ching Yun Univ, Dept Comp Sci & Informat Engn, Chungli 320, Taiwan
[3] Feng Chia Univ, Dept Informat Engn & Comp Sci, Taichung 407, Taiwan
关键词
Finite fields; Cryptography; Fault detection; Double parity prediction; Side-channel attack; Normal basis; OMURA PARALLEL MULTIPLIER; FINITE-FIELDS;
D O I
10.1007/s11265-009-0361-4
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Successful implementation of elliptic curve cryptographic systems primarily depends on the efficient and reliable arithmetic circuits for finite fields with very large orders. Thus, the robust encryption/decryption algorithms are elegantly needed. Multiplication would be the most important finite field arithmetic operation. It is much more complex compared to the finite field addition. It is also frequently used in performing point operations in elliptic curve groups. The hardware implementation of a multiplication operation may require millions of logic gates and may thus lead to erroneous outputs. To obtain reliable cryptographic applications, a novel concurrent error detection (CED) architecture to detect erroneous outputs in multiplexer-based normal basis (NB) multiplier over GF (2(m)) using the parity prediction scheme is proposed in this article. Although various NB multipliers, depending on alpha alpha(2i) = Sigma(m-1)(j=0) t(i,j)alpha(2i), have different time and space complexities, NB multipliers will have the same structure if they use a parity prediction function. By using the structure of the proposed CED NB multiplier, a CED scalable multiplier over composite fields with 100% error detection rate is also presented.
引用
收藏
页码:233 / 246
页数:14
相关论文
共 50 条
  • [21] Concurrent error detection in a bit-parallel systolic multiplier for dual basis of GF(2m)
    Lee, CY
    Chiou, C
    Lin, JM
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2005, 21 (05): : 539 - 549
  • [22] Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m)
    Chiou-Yng Lee
    Che Wun Chiou
    Jim-Min Lin
    Journal of Electronic Testing, 2005, 21 : 539 - 549
  • [23] Performance Analysis of Gaussian Normal Basis GF (2m) Serial Multipliers and Inverters
    Puligunta, Mahidhar
    El-Razouk, Hayssam
    2021 IEEE 11TH ANNUAL COMPUTING AND COMMUNICATION WORKSHOP AND CONFERENCE (CCWC), 2021, : 738 - 746
  • [24] Efficient digit-serial normal basis multipliers over GF(2M)
    Reyhani-Masoleh, A
    Hasan, MA
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 781 - 784
  • [25] Self-Checking Gaussian Normal Basis Multiplier over GF(2m) Using Multiplexer Approach
    Chiou, Che Wun
    Lin, Jim-Min
    Chang, Hung Wei
    Liang, Wen-Yew
    Wang, Jenq-Haur
    Yeh, Yun-Chi
    2012 SIXTH INTERNATIONAL CONFERENCE ON GENETIC AND EVOLUTIONARY COMPUTING (ICGEC), 2012, : 505 - 508
  • [26] On-Line Error Detection for Bit-Serial Multipliers in GF(2m)
    Sebastian Fenn
    Michael Gossel
    Mohammed Benaissa
    David Taylor
    Journal of Electronic Testing, 1998, 13 : 29 - 40
  • [27] On-line error detection for bit-serial multipliers in GF(2m)
    Fenn, S
    Gossel, M
    Benaissa, M
    Taylor, D
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1998, 13 (01): : 29 - 40
  • [28] MULTIPLE ERROR DETECTION AND CORRECTION OVER GF(2m) USING NOVEL CROSS PARITY CODE
    Sundary, M. Selva
    Logisvary, V.
    PROCEEDINGS OF THE 10TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO'16), 2016,
  • [29] Error-correcting codes for concurrent error correction in bit-parallel systolic and scalable multipliers for shifted dual basis of GF(2m)
    Lee, Chiou-Yng
    Meher, Pramod Kumar
    Chen, Yung-Hui
    Journal of Computers, 2011, 22 (03): : 37 - 52
  • [30] A novel architecture for Galois fields GF(2m) multipliers based on Mastrovito scheme
    Petra, Nicola
    De Caro, Davide
    Strollo, Antonio G. M.
    IEEE TRANSACTIONS ON COMPUTERS, 2007, 56 (11) : 1470 - 1483