A novel systolic array processor with dynamic dataflows

To improve the performance of systolic array processors, this paper designs and implements a novel architecture which supports dynamic dataflows. First, we design three typical systolic array processors, including the output stationary, weight stationary, and input stationary systolic array. Second, we detailedly evaluate the performance of these processors, and find that none of them always perform best in all environments. Finally, based on the characteristics of three different dataflows, this paper designs a novel systolic array processor with dynamic dataflows. The experimental results show that the proposed systolic array processor achieves the best performance for a variety of computing environments.