A systolic array RLS processor

被引：0
|
作者：
Asai, T. [1 ]
Matsumoto, T. [1 ]
机构：
[1] Wireless Laboratories, NTT Do-CoMo, Inc., Yokosuka-shi 239-8536, Japan
来源：
| 2001年 / Institute of Electronics, Information and Communication, Engineers, IEICE卷 / E85-B期
关键词：
Recursive least-squares (RLS) processors;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [1] A systolic array RLS processor
    Asai, T
    Matsumoto, T
    [J]. IEICE TRANSACTIONS ON COMMUNICATIONS, 2001, E84B (05) : 1356 - 1361
  • [2] A systolic array RLS processor
    Asai, T
    Matsumoto, T
    [J]. 2000 IEEE 51ST VEHICULAR TECHNOLOGY CONFERENCE, PROCEEDINGS, VOLS 1-3, 2000, : 2247 - 2251
  • [3] SYSTOLIC ARRAY PROCESSOR IMPLEMENTATION
    SYMANSKI, JJ
    [J]. PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1981, 298 : 27 - 32
  • [4] WARP - A PROGRAMMABLE SYSTOLIC ARRAY PROCESSOR
    KUNG, HT
    MENZILCIOGLU, O
    [J]. PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1984, 495 : 130 - 136
  • [5] SYSTOLIC ARRAY PROCESSOR FOR MVDR BEAMFORMING
    MCWHIRTER, JG
    SHEPHERD, TJ
    [J]. IEE PROCEEDINGS-F RADAR AND SIGNAL PROCESSING, 1989, 136 (02) : 75 - 80
  • [6] A novel systolic array processor with dynamic dataflows
    Wang, Bo
    Ma, Sheng
    Zhu, Guoyi
    Yi, Xiao
    Xu, Rui
    [J]. INTEGRATION-THE VLSI JOURNAL, 2022, 85 : 42 - 47
  • [7] A VECTORIZED SYSTOLIC ARRAY FOR PARALLEL WEIGHT EXTRACTION OF BLOCK RLS
    SAKAI, H
    [J]. INTERNATIONAL JOURNAL OF ADAPTIVE CONTROL AND SIGNAL PROCESSING, 1994, 8 (05) : 475 - 482
  • [8] Multipath suppression performance of an adaptive array antenna with a systolic array processor
    Ohmiya, Manabu
    Kawabata, Tatsuya
    Ogawa, Yasutaka
    Itoh, Kiyohiko
    [J]. Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi), 1993, 76 (11): : 95 - 104
  • [9] A JOSEPHSON SYSTOLIC ARRAY PROCESSOR FOR MULTIPLICATION ADDITION OPERATIONS
    MORISUE, M
    LI, FQ
    TOBITA, M
    KANEKO, S
    [J]. IEEE TRANSACTIONS ON MAGNETICS, 1991, 27 (02) : 2855 - 2858
  • [10] A systolic processor array for the quadrant interlocking elimination method
    Evans, DJ
    [J]. INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS, 2000, 74 (01) : 29 - 44
12345