A systolic processor array for the quadrant interlocking elimination method

被引：0
|
作者：
Evans, DJ [1 ]
机构：
[1] Nottingham Trent Univ, Dept Comp, Nottingham, England
来源：
INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS | 2000年 / 74卷 / 01期
关键词：
systolic array; linear equations solver; Quadrant Interlocking Elimination;
D O I：
10.1080/00207160008804920
中图分类号：
O29 [应用数学];
学科分类号：
070104 ;
摘要：
In this paper a systolic array is presented for the solution of linear equations occurring in scientific and engineering calculations. The new systolic array is based on the parallel Quadrant Interlocking Elimination method of Evans and Hadjidimos [1].
引用
收藏
页码：29 / 44
页数：16
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