A 5 ps resolution, 8.6 ns delay range digital delay line using combinatorial redundancy

被引：0

作者：

Van den Dries, Thomas ^{[1
]}

Ingelberts, Hans ^{[1
]}

Boulanger, Sven ^{[1
]}

Kuijk, Maarten ^{[1
]}

机构：

[1] Vrije Univ Brussel, Brussels, Belgium

来源：

2019 15TH CONFERENCE ON PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME) | 2019年

关键词：

D O I：

10.1109/prime.2019.8787802

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel digital delay line architecture is presented, which is able to achieve a high resolution of 5 ps and a wide delay range of 8.6 ns simultaneously. It does so by combining elements of digital and analog delay locked loops and uses a replica circuit to compensate for temperature variations. Furthermore, accurate and precise delay steps with 3.8 ps RMS jitter are obtained by using combinatorial redundancy. Its overall performance is superior to state-of-the-art approaches, which make a trade-off for at least one of the performance metrics.

引用

页码：21 / 24

页数：4

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