DESIGN AND FPGA IMPLEMENTATION OF BINARY SQUARER USING VEDIC MATHEMATICS

被引：0

作者：

Sriraman, L. ^{[1
]}

Kumar, K. Saravana ^{[1
]}

Prabakar, T. N. ^{[1
]}

机构：

[1] Oxford Engn Coll, Dept Elect & Commun Engn, Tiruchirappalli, Tamil Nadu, India

来源：

2013 FOURTH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATIONS AND NETWORKING TECHNOLOGIES (ICCCNT) | 2013年

关键词：

Squarer; Vedic Mathematics; Ekadhikena Purvena; FPGA; Duplex squarer;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a squarer based on Vedic mathematics is proposed. Vedic mathematics is one of the ancient Indian mathematics which contains sixteen sutras. These sutras can be used to solve problems in any branch of Mathematics in a faster way. The proposed squarer is based on sutra called Ekadhikena Purvena. It means that "one more than the previous". This sutra is used for finding the square of decimal numbers ending with '5'. In this paper this sutra is generalized and used for squaring of binary numbers. The proposed squarer is compared with duplex squarer for 8, 16 and 32-bit cases in Cyclone III FPGA EP3C16F484C6. The proposed squarer saves area by almost 50% and reduces delay by 50% when compared with duplex squarer in 32-bit case.

引用

下载

页数：5

共 50 条

[31] Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation
Thamizharasan, V.
Parthipan, V.
SCIENTIFIC REPORTS, 2024, 14 (01)
[32] Design and FPGA Implementation of Optimized 32-Bit Vedic Multiplier and Square Architectures
Sharma, Richa
Kaur, Manjit
Singh, Gurmohan
2015 INTERNATIONAL CONFERENCE ON INDUSTRIAL INSTRUMENTATION AND CONTROL (ICIC), 2015, : 960 - 964
[33] Design and Verification of 16 bit RISC Processor Using Vedic Mathematics
Yadav, Ankita
Bendre, Varsha
2021 INTERNATIONAL CONFERENCE ON EMERGING SMART COMPUTING AND INFORMATICS (ESCI), 2021, : 759 - 764
[34] High Speed Multiplier Implementation Based on Vedic Mathematics
Meghana, V.
Sandhya, S.
Aparna, R.
Gururaj, C.
2015 INTERNATIONAL CONFERENCE ON SMART SENSORS AND SYSTEMS (IC-SSS 2015), 2015,
[35] Physical Level Design of Floating Point Multiplier using Vedic Mathematics
Srinivasan, S., V
Rajak, Abdul A. R.
2015 INTERNATIONAL CONFERENCE ON EMERGING RESEARCH IN ELECTRONICS, COMPUTER SCIENCE AND TECHNOLOGY (ICERECT), 2015, : 468 - 471
[36] Low power squarer design using Ekadhikena Purvena on 28nm FPGA
Jaypee Institute of Information Technology, Noida, India
不详
Int. J. Control Autom., 5 (281-288):
[37] Design and Analysis of ALU: Vedic Mathematics Approach
Rawat, Garima
Rathore, Khyati
Goyal, Siddharth
Kala, Shefali
Mittal, Poornima
2015 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION & AUTOMATION (ICCCA), 2015, : 1372 - 1376
[38] Series Computation Using Vedic Mathematics
Mehra, Anu
Verma, Vinay
Rajput, Sachin Kumar
Tyagi, Devyani
2016 CONFERENCE ON ADVANCES IN SIGNAL PROCESSING (CASP), 2016, : 504 - 506
[39] Design and Implementation of 64 Bit Multiplier using Vedic Algorithm
Jais, Amish
Palsodkar, Prasanna
2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), VOL. 1, 2016, : 775 - 779
[40] Design and Implementation of PN Sequence Generator using Vedic Multiplication
Jamgade, Roshni
Ambatkar, Shrikant
Kakde, Sandeep
2015 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTER ENGINEERING AND APPLICATIONS (ICACEA), 2015, : 84 - 87

← 1 2 3 4 5 →