SAT Encoding-based Verification of Sneak Path Problem in Via-switch FPGA

被引：0

作者：

Doi, Ryutaro ^{[1
,2
]}

Hashimoto, Masanori ^{[1
]}

机构：

[1] Osaka Univ, Grad Sch Informat Sci & Technol, Dept Informat Syst Engn, Suita, Osaka, Japan

[2] Japan Soc Promot Sci, Tokyo, Japan

来源：

2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI) | 2018年

关键词：

D O I：

10.1109/ISVLSI.2018.00084

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

FPGA that introduces via-switches, a kind of non-volatile resistive RAMs, for crossbar implementation is drawing attention due to higher integration density and performance. However, programming those switches arbitrarily in a crossbar is not trivial since a programming voltage must be given through signal wires that are shared by multiple via-switches. Consequently, depending on the previous programming status, unintentional switch programming may occur due to signal detour, which is called sneak path problem. This paper encodes programming operations in via-switch based crossbar into a satisfiability problem and rigidly verifies the sneak path problem. Verification results show that sneak path problems can be solved by imposing a specific programming constraint.

引用

页码：429 / 434

页数：6

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