Lithography-Friendly Analog Layout Migration

被引：0
|
作者：
Dong, Xuan [1 ]
Zhang, Lihong [1 ]
机构：
[1] Mem Univ Newfoundland, Dept Elect & Comp Engn, Fac Engn & Appl Sci, St John, NF, Canada
来源：
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2015年
关键词：
lithographic effects; spot defect; analog IP; layout reuse; OPTIMIZATION;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Lithographic effects have long been a primary yield consideration during integrated circuit (IC) manufacture. Especially the random spot defects may easily lead to functional failures across the chip. In this paper, a lithography-friendly analog layout migration flow is proposed. The optimization is achieved by intelligent redundant space utilization, which includes wire widening and wire shifting in order to minimize global probability of failure. We also propose a way of effectively reduce the probability of failure by a reasonable chip area compromise. Our experimental results indicate significant yield improvement for both short and open type faults.
引用
收藏
页码：2137 / 2140
页数：4
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