A low-voltage swing latch for reduced power dissipation in high-frequency microprocessors

We report in this paper a new low-swing latch (LSL) for low-power applications. Unlike the conventional transmission gate latch, the LSL allows reduced voltage on the clock inputs. Therefore the local clock buffer (LCB) can use reduced swing to save power while all other circuits are running at nominal voltage. We have implemented an accumulator loop experiment in an early version of IBM's 90 nm SOI technology [1] on a testchip. The experiment consists of an adder and a decrementer surrounded by latches to mimic logic between pipeline stages. Side-by-side comparisons between the transmission gate latch and LSL are designed to illustrate the superior power-performance tradeoff of the LSL approach. Hardware measurements have shown 12% AC power saving in 90nm technology.