Optimization of 3D IC stacking chip on molded encapsulation process: a response surface methodology approach

The stress concentration and deformation of the 3D stacked IC structures can be minimized with an optimal design of the integrated circuit (IC) using a response surface methodology. The geometrical and process parameters (i.e., A = inlet pressure, B = solder bump standoff height, C = chip thickness, and D = aspect ratio) were optimized via a central composite design (CCD) for the molded encapsulation process. The fluid/structure interaction (FSI) aspects were considered in the optimization of the molded encapsulation process. The separate effects of the independent variables and their interactions were studied. The calculated empirical models were carried out and well validated with the simulation results. The optimum geometrical and process parameters of the 3D stacked IC package with perimeter solder bump arrangement were characterized as follows: inlet condition of 3.65 MPa, 150 mu m of solder bump standoff height, 250 mu m of chip thickness, and 2.1 of aspect ratio. The outcomes herein may significantly contribute to the advancement of microelectronic industries.