A 188-size 2.1mm2 Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System

被引：0
|
作者：
Wong, Cheng-Chi [1 ]
Lee, Yung-Yu [1 ]
Chang, Hsie-Chia [1 ]
机构：
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan
来源：
2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2009年
关键词：
3GPP LTE; turbo decoder; and QPP interleaver;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a three-stage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm(2) chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.
引用
收藏
页码：288 / 289
页数：2
相关论文
共 11 条
  • [1] Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System
    Wong, Cheng-Chi
    Chang, Hsie-Chia
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2010, 57 (07) : 566 - 570
  • [2] Implementation of A High-Speed Parallel Turbo Decoder for 3GPP LTE Terminals
    Wu, Di
    Asghar, Rizwan
    Huang, Yulin
    Liu, Dake
    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 481 - 484
  • [3] Efficient Highly-Parallel Turbo Decoder for 3GPP LTE-Advanced
    Lin, Jing-Shiun
    Shieh, Ming-Der
    Liu, Chung-Yen
    Yang, Der-Wei
    2015 International symposium on VLSI Design, Automation and Test (VLSI-DAT), 2015,
  • [4] A 1.5 Gb/s Highly Parallel Turbo Decoder for 3GPP LTE/LTE-Advanced
    Chen, Yun
    Chen, Xubin
    Guo, Zhiyuan
    Zeng, Xiaoyang
    Huang, Defeng
    IEICE TRANSACTIONS ON COMMUNICATIONS, 2013, E96B (05) : 1211 - 1214
  • [5] Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder
    Sun, Yang
    Cavallaro, Joseph R.
    INTEGRATION-THE VLSI JOURNAL, 2011, 44 (04) : 305 - 315
  • [6] A 516Mb/s 0.2nJ/bit/iter Variable-Block-Size Turbo Decoder for 3GPP LTE-A System
    Hsieh, Chi-Hsuan
    Lee, Ming-Yong
    Huang, Yuan-Hao
    2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2012, : 343 - 346
  • [7] A 10.37 mm2 675 mW reconfigurable LDPC and Turbo encoder and decoder for 802.11n, 802.16e and 3GPP-LTE
    Naessens, F.
    Derudder, V.
    Cappelle, H.
    Hollevoet, L.
    Raghavan, P.
    Desmet, M.
    AbdelHamid, A. M.
    Vos, I.
    Folens, L.
    O'Loughlin, S.
    Singirikonda, S.
    Dupont, S.
    Weijers, J-W
    Dejonghe, A.
    Van der Perre, L.
    2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2010, : 213 - 214
  • [8] A 0.077 to 0.168 nJ/bit/iteration Scalable 3GPP LTE Turbo Decoder with an Adaptive Sub-Block Parallel Scheme and an Embedded DVFS Engine
    Cheng, Chih-Chi
    Tsai, Yi-Min
    Chen, Liang-Gee
    Chandrakasan, Anantha P.
    IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, 2010,
  • [9] Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems
    Shih, Xin-Yu
    Chou, Hong-Ru
    ICT EXPRESS, 2018, 4 (03): : 144 - 148
  • [10] A 691 Mbps 1.392mm2 Configurable Radix-16 Turbo Decoder ASIC for 3GPP-LTE and WiMAX Systems in 65nm CMOS
    Chen, Xubin
    Chen, Yun
    Li, Yi
    Huang, Yuebin
    Zeng, Xiaoyang
    PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2013, : 157 - 160
12