A 691 Mbps 1.392mm2 Configurable Radix-16 Turbo Decoder ASIC for 3GPP-LTE and WiMAX Systems in 65nm CMOS

被引：0

作者：

Chen, Xubin ^{[1
]}

Chen, Yun ^{[1
]}

Li, Yi ^{[1
]}

Huang, Yuebin ^{[1
]}

Zeng, Xiaoyang ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China

来源：

PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2013年

关键词：

Turbo decoder; radix-16; interleaver; 4G mobile communication; LTE; WiMAX; ASIC implementation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a unified parallel radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems. A radix-16 decoding for both binary and duo-binary turbo codes is proposed to reduce complexity as well as critical path delay. In addition, the two distinct interleavers in the standards are implemented with low-complexity address generator and barrel shift networks. Furthermore, quad-bank memory partition facilitates parallel radix-16 decoding without address conflict. Fabricated in TSMC 65nm CMOS process, the ASIC attains 691Mbps throughput running at 512MHz and 5.5 iterations. For the 326.4Mbps LTE peak data rate, it consumes only 193mW at 0.9V supply voltage with unprecedented energy efficiency of 0.108nJ/bit/iteration.

引用

页码：157 / 160

页数：4