Effect of channel positioning on the 1/f noise in silicon-on-insulator metal-oxide-semiconductor field-effect transistors

p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated on silicon-on-insulator (SOI) substrates with an ultrathin (similar to 20 nm) lightly p-doped Si body were found to show about an order of magnitude lower 1/f noise than that in conventional bulk Si pMOSFETs when biased in strong inversion. In order to investigate the origin of the 1/f noise and find an explanation for the 1/f noise reduction, the 1/f noise in the SOI devices was studied as a function of the back gate voltage. The 1/f noise was found to increase with increasing back gate voltage, which acts to push the carriers closer towards the front gate oxide interface. The average distance of the inversion carriers from the gate oxide interface was obtained from simulations and used to interpret the 1/f noise behavior. The Hooge parameter, extracted for several different 1/f noise experiments where one or two terminal voltages were varied, exhibited a general behavior similar for both the SOI and bulk Si pMOSFETs. The Hooge parameter was shown to increase markedly when the average carrier-oxide separation is around 2 nm. Possible explanations of the results were discussed in terms of the mobility fluctuation noise model. (c) 2007 American Institute of Physics.