Differential Input Area Efficient Current Comparator

被引：0

作者：

Serazetdinov, A. R. ^{[1
]}

Atkin, E., V ^{[1
]}

Khokhlov, K. O. ^{[2
]}

机构：

[1] Natl Res Nucl Univ MEPhI, Moscow, Russia

[2] Ural Fed Univ, Yekateringurg, Russia

来源：

PHYSICS, TECHNOLOGIES AND INNOVATION (PTI-2019) | 2019年 / 2174卷

关键词：

D O I：

10.1063/1.5134401

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Differential input area efficient current comparator for multichannel detector (sensor) applications is presented. Comparator consists of current preamplifier, hysteresis latch, amplifier-voltage limiter and output low-voltage to CMOS translator, having built-in polarity selection switch. The latch geometry was chosen to feature non-zero hysteresis and minimum size. The key features of the proposed solution are low voltage swing before translator, low power consumption and simplicity. The comparator was developed in UMC 180 nm MMRF CMOS process. It consumes less than 60 mu W at 1.8 V. Its layout cell was designed as an area efficient one and occupies 1200 mu m(2).

引用

页数：5

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