Highly Robust Nanoscale Planar Double-Gate MOSFET Device and SRAM Cell Immune to Gate-Misalignment and Process Variations

被引：0

作者：

Sachid, Angada B. ^{[1
]}

Kulkarni, Giri S. ^{[1
]}

Baghini, Maryam S. ^{[1
]}

Sharma, Dinesh K. ^{[1
]}

Rao, V. Ramgopal ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Ctr Excellence Nanoelect, Bombay 400076, Maharashtra, India

来源：

2009 2ND INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY | 2009年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Gate misalignment and process variations are important challenges in sub-20 nm gate length planar double-gate (DG) MOSFET devices For the first time, we demonstrate a misalignment- and process variations-aware device optimization strategy for a DG-MOSFET Using underlaps and high-kappa offset-spacers, we show that the robustness of the device to gate misalignment and process variations can be improved. A standard 6T-SRAM cell designed using the optimized devices shows better read and hold static noise margins, and lower variations in SNM and leakage power compared to a conventional DG-MOSFET.

引用

页码：13 / 16

页数：4

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