Differential current mode serial link for 2 Gb/s in GaAs technology

被引:0
|
作者
Esper-Chaín, R [1 ]
Tobajas, F [1 ]
Sarmiento, R [1 ]
机构
[1] Inst Univ Microelect Aplicada, E-35017 Las Palmas Gran Canaria, Spain
关键词
high-speed serial links; differential current model; power dissipation;
D O I
10.1016/S0026-2692(02)00116-7
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Today's data communication systems are demanding increasing off-chip data rates. To satisfy this demand, high-speed serial links are used, saving area and power dissipation compared to highly parallel buses. However, power dissipation and noise generated by this system is still a critical issue. In this article, a novel approach using differential current mode is presented, which combines low power dissipation with low noise generated due to the reduced power transmission. (C) 2002 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:1107 / 1114
页数:8
相关论文
共 50 条
  • [31] A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS
    Zhang, Bo
    Khanoyan, Karapet
    Hatamkhani, Hamid
    Tong, Haitao
    Hu, Kangmin
    Fallahi, Siavash
    Abdul-Latif, Mohammed
    Vakilian, Kambiz
    Fujimori, Ichiro
    Brewster, Anthony
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (12) : 3089 - 3100
  • [32] A 0.18 μm CMOS 12 Gb/s 10-PAM Serial Link Transmitter
    Song, Bongsub
    Kim, Kwangsoo
    Burm, Jinwook
    IEICE TRANSACTIONS ON ELECTRONICS, 2011, E94C (11): : 1787 - 1793
  • [33] A 13.5-mW 10-Gb/s 4-PAM Serial Link Transmitter in 0.13-μm CMOS Technology
    Song, Bongsub
    Kim, Kyunghoon
    Lee, Junan
    Chung, Jinil
    Choi, Youngjung
    Burm, Jinwook
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2014, 61 (09) : 646 - 650
  • [34] Common-mode current harmonics on differential pair cable shields operating in a regime as high as 2.125 Gb/s
    Knighten, JL
    Smith, NW
    Fan, J
    DiBene, JT
    Hoeft, LO
    2001 IEEE EMC INTERNATIONAL SYMPOSIUM, VOLS 1 AND 2, 2001, : 47 - 51
  • [35] A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery
    Liao, Chih-Fan
    Liu, Shen-Iuan
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (11) : 2492 - 2502
  • [36] 10+Gb/s 90nm CMOS serial link demo in CBGA package
    Rylov, S
    Reynolds, S
    Storaska, D
    Floyd, B
    Kapur, M
    Zwick, T
    Gowda, S
    Sorna, M
    PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2004, : 27 - 30
  • [37] A 5-Gb/s Serial-Link Redriver With Adaptive Equalizer and Transmitter Swing Enhancement
    Liu, Haiqi
    Wang, Yanbo
    Xu, Changxi
    Chen, Xinqing
    Lin, Lei
    Yu, Yue
    Wang, Wei
    Majumder, Amit
    Chui, Gene
    Brown, Dave
    Fang, Al
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (04) : 1001 - 1011
  • [38] 10+Gb/s 90-nm CMOS serial link demo in CBGA package
    Rylov, S
    Reynolds, S
    Storaska, D
    Floyd, B
    Kapur, M
    Zwick, T
    Gowda, S
    Sorna, M
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (09) : 1987 - 1991
  • [39] A 33 Gb/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13μm BiCMOS technology for serial link
    Zhang, Yinhang
    Hu, Qingsheng
    IEICE ELECTRONICS EXPRESS, 2018, 15 (04):
  • [40] A Fully Integrated 0.13-μm CMOS 40-Gb/s Serial Link Transceiver
    Kim, Jeong-Kyoum
    Kim, Jaeha
    Kim, Gyudong
    Jeong, Deog-Kyoon
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (05) : 1510 - 1521