A Novel design of a high speed hysteresis-based comparator in 90-nm CMOS technology

被引：0

作者：

Nanda, Satyabrata ^{[1
]}

Panda, Avipsa S. ^{[2
]}

Moganti, G. L. K. ^{[3
]}

机构：

[1] Pune Inst Aviat Technol, Dept Avionics, Pune, Maharashtra, India

[2] Trident Acad Technol, Dept Elect & Telecommun Engn, Bhubaneswar, Odisha, India

[3] KIIT Univ, Sch Elect Engn, Bhubaneswar, Odisha, India

来源：

2015 IEEE INTERNATIONAL CONFERENCE ON INFORMATION PROCESSING (ICIP) | 2015年

关键词：

comparator; noisy output; analog-to-digital conversion; hysteresis; noisy comparator;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Analog-to-digital circuit converts an analog signal having continuous-time and continuous-amplitude to a discrete time and discrete-amplitude digital signal. A comparator is a vital block in any analog-to-digital circuit. The comparators play a crucial part in the analog to digital conversion. This paper puts forth the design of hysteresis comparator in 90-nm CMOS technology. The proposed comparator reduces the occurrence of noisy output and has high speed, in comparison to the conventional comparator. The circuit design and analysis has been done using Cadence.

引用

页码：388 / 391

页数：4

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