Integration of an advanced 3D TSV with the 7nm EUV logic process

被引：0
|
作者：
Ding, Shaofeng [1 ]
Choi, Yun Ki [1 ]
Kim, Jihyung [1 ]
Kang, Minguk [1 ]
Seo, Dongju [1 ]
Yoo, Haeri [1 ]
Lee, Joon Nyung [1 ]
Oh, Jae Hee [1 ]
Park, Won Ji [1 ]
Masuoka, Yuri Y. [1 ]
Ahn, Jeong Hoon [1 ]
Kwon, S. D. [1 ]
机构：
[1] Samsung Elect Foundry Business, PA Team, Yongin, South Korea
来源：
2020 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC) | 2020年
关键词：
3D TSV; BEOL; KOZ; 7nm;
D O I：
10.1109/IITC47697.2020.9515673
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The integration of a high aspect ratio Through Silicon Via (TSV) process with the EUV 7nm logic process was developed for the first time. The TSV and MOL to BEOL interface process was developed and the BEOL Via on TSV and MOL structure was evaluated. TSV to BEOL and device proximity study was performed by placing TSVs at various keepout zone (KOZ) distances and different TSV orientations to the devices. The TSV KOZ split results for BEOL test structures showed no recognizable via/metal open/short yields loss nor performance degradation. The TSV KOZ splits results for device showed different performance variation related to both the device split parameters and TSV locations, nevertheless the variation laid within the process specification.
引用
收藏
页码：145 / 147
页数：3
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