Efficient synthesis of speed-independent combinational logic circuits

被引：8

作者：

Toms, W. B. ^{[1
]}

Edwards, D. A. ^{[1
]}

机构：

[1] Univ Manchester, Dept Comp Sci, Manchester M13 9PL, Lancs, England

来源：

ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2005年

关键词：

D O I：

10.1145/1120725.1120782

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Speed-Independent synthesis of combinational logic datapath, circuits using tools such as Petrdy is often inefficient or infeasible because such circuits typically contain many concurrent inputs and independent outputs. This paper presents a practical method for generating arbitrary combinational logic circuits, using a sub-class of speed-indepehdent circuits known as Strongly-Indicating circuits, without the need to verify the speed-independence of the implementation through construction of a state-graph or other method.

引用

页码：1022 / 1026

页数：5

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