Decoupling Capacitor Estimation and Allocation using Optimization Techniques for Power Supply Noise Reduction in System-on-Chip

被引：2
|
作者：
Mitra, Partha [1 ]
Bhaumik, Jaydeb [2 ]
Sarkar, Angsuman [3 ]
机构：
[1] Maulana Abul Kalam Azad Univ Technol, Dept Elect & Commun Engn, Haringhata 741249, India
[2] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India
[3] Kalyani Govt Engn Coll, Dept Elect & Commun Engn, Kalyani 741235, W Bengal, India
来源：
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2021年 / 37卷 / 01期
关键词：
Computer aided design (CAD); Decoupling capacitor (decap); Power distribution network (PDN); Particle swarm optimization (PSO); Symbiotic organism search (SOS);
D O I：
10.1007/s10836-021-05931-7
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This article examines the signal integrity problem arising due to resistive drop, inductive noise and electro- migration, causing voltage fluctuations known as supply noise in an integrated circuit. Insertion of decoupling capacitor is a commonly used technique for reducing the supply noise. In this article symbiotic organism search (SOS) algorithm is used to estimate the decap. Another relevant issue addressed is the distribution of the decap over the chip. To get the best possible results in the post-layout stage pruning technique is used for partitioning and particle swarm optimization (PSO) algorithm is applied in the floorplanning stage. The purpose of this work is to reduce the supply noise without much affecting other design parameters of the chip. Simulation results show that supply noise has been reduced by up to 74.07% and the decap budget has been reduced by up to 37.4%. This approach can be used for any system-on-chip.
引用
收藏
页码：151 / 155
页数：5
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