A 12-bit 200MS/s Pipelined-SAR ADC in 65-nm CMOS with 61.9 dB SNDR

被引：0
|
作者：
Liu, Haizhu [1 ]
Liu, Maliang [1 ]
Zhu, Zhangming [1 ]
机构：
[1] Xidian Univ, Sch Microelect, Xian, Shaanxi, Peoples R China
来源：
2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2019年
基金：
中国国家自然科学基金;
关键词：
Pipelined-SAR ADC; MDAC; hybrid architecture;
D O I：
10.1109/edssc.2019.8754022
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a 12-bit 200MS/s PipelinedSAR hybrid architecture ADC with a 3.5-bit MDAC for the first stage and a 9-bit SAR ADC for the second stage. In the MDAC, a low-power high DC-gain class-AB residue amplifier is proposed to achieve 80dB DC-gain and 0.8GHz unity-gain-bandwidth (UGB). In the SAR ADC, two techniques are applied to accelerate the comparison speed to meet the requirement of high-speed ADC. Fabricated in a 65nm CMOS process, the ADC occupies an area of 0.21 mm(2) and consumes a power of 7.3 mW. The measured Nyquist SFDR and SNDR are 71.2 dB and 61.9 dB at 200 MS/s. The ADC achieves a FoM of 35.6 fJ/conversion-step.
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页数：2
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