Design of power-efficient CMOS based oscillator circuit with varactor tuning control

被引:1
|
作者
Dwivedi, Dileep [1 ,2 ]
Kumar, Manoj [1 ,2 ]
Niranjan, Vandana [3 ]
机构
[1] Univ Sch Informat, Commun & Technol, New Delhi, India
[2] Guru Gobind Singh Indraprastha Univ, New Delhi, India
[3] Indira Gandhi Delhi Tech Univ Women, Dept ECE, New Delhi, India
来源
SN APPLIED SCIENCES | 2021年 / 3卷 / 04期
关键词
Delay cell; I-MOS varactor; MOS current mode logic; Phase noise; Voltage controlled oscillator;
D O I
10.1007/s42452-021-04501-y
中图分类号
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号
07 ; 0710 ; 09 ;
摘要
This paper presents a low-power, wide tuning range CMOS voltage-controlled oscillator with MCML (MOS current mode logic) differential delay cell. Voltage controlled oscillator (VCO) circuit is designed in TSMC 0.25 mu m CMOS process. To achieve the broad frequency range concept of variable capacitance is employed in the proposed VCO circuit. Source/drain tuning voltage (V-tune) and body bias voltage (V-b) of I-MOS varactor are used to achieve variable capacitance at different I-MOS varactor widths (W). The dual control voltage of I-MOS varactor results in a tuning range from 0.528 GHz to 2.014 GHz. VCO's figure of merit (FoM) is 152.13 dBc/Hz with phase noise of -93.77 dBc/Hz at 1 MHz offset from the oscillation frequency. The proposed VCO dissipates maximum power of 3.127 mW.
引用
收藏
页数:8
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