共 50 条
- [22] Reconfigurable Hardware Implementation of Gigabit UDP/IP Stack Based on Spartan-6 FPGA [J]. 2014 6TH INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY AND ELECTRICAL ENGINEERING (ICITEE), 2014, : 370 - 375
- [24] Design of linear algebra hardware accelerators dedicated to implementation in FPGA devices [J]. PRZEGLAD ELEKTROTECHNICZNY, 2011, 87 (10): : 155 - 158
- [25] Kernel-as-a-Service: A Serverless Programming Model for Heterogeneous Hardware Accelerators [J]. PROCEEDINGS OF THE 24TH ACM/IFIP INTERNATIONAL MIDDLEWARE CONFERENCE, MIDDLEWARE 2023, 2023, : 192 - 206
- [26] An efficient hardware implementation of sequential stack decoding of binary block codes [J]. 2015 IEEE 5TH INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - BERLIN (ICCE-BERLIN), 2015, : 135 - 138
- [27] Hardware-Software Co-Design Based Obfuscation of Hardware Accelerators [J]. 2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019), 2019, : 549 - 554
- [28] Enhanced functionality for hardware-based FDTD accelerators [J]. APPLIED COMPUTATIONAL ELECTROMAGNETICS SOCIETY JOURNAL, 2007, 22 (01): : 39 - 46
- [29] Usage-Based RTL Subsetting for Hardware Accelerators [J]. 2022 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, ICCAD, 2022,
- [30] Batched matrix computations on hardware accelerators based on GPUs [J]. INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS, 2015, 29 (02): : 193 - 208