An efficient hardware implementation of sequential stack decoding of binary block codes

被引：0
|
作者：
Freudenberger, Juergen [1 ]
Wegmann, Thomas
Spinner, Jens
机构：
[1] Univ Appl Sci, HTWG Konstanz, Constance, Germany
来源：
2015 IEEE 5TH INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - BERLIN (ICCE-BERLIN) | 2015年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This work proposes an efficient hardware implementation of sequential stack decoding of binary block codes. The decoder can be applied for soft input decoding for generalized concatenated (GC) codes. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes. In order to enable soft input decoding for the inner BCH block codes, a sequential stack decoding algorithm is used.
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页码：135 / 138
页数：4
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