A 1GHz dual-loop microprocessor PLL with instant frequency shifting

被引：1
|
作者：
Bhagwan, R
Rogers, A
机构：
来源：
1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS | 1997年 / 40卷
关键词：
D O I：
10.1109/ISSCC.1997.585409
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：336 / 337
页数：2
相关论文
共 50 条
  • [11] 1GHZ FREQUENCY-DIVIDER
    DIJKSTRA, W
    ELECTRONICS WORLD & WIRELESS WORLD, 1994, (1694): : 66 - 66
  • [12] An Array of Coherent Sources Based on Novel Dual-Loop PLL Infrastructure
    Tang, Chengcheng
    Xue, Quan
    IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2013, 60 (11) : 5337 - 5347
  • [13] An Integral Path Self-Calibration Scheme for a Dual-Loop PLL
    Ferriss, Mark
    Plouchart, Jean-Olivier
    Natarajan, Arun
    Rylyakov, Alexander
    Parker, Ben
    Tierno, Jose A.
    Babakhani, A.
    Yaldiz, Soner
    Valdes-Garcia, Alberto
    Sadhu, Bodhisatwa
    Friedman, Daniel J.
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (04) : 996 - 1008
  • [14] A Dual-loop Phase Locked Loop with Frequency to Voltage Converter
    Jin, Xuefan
    Kwon, Kee-Won
    Choi, Young-Shig
    Chun, Jung-Hoon
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2019, 19 (03) : 292 - 299
  • [15] Design and Modeling of PLL based 1GHz Frequency Synthesizer using 0.35μm SiGeBiCMOS Process
    Channayya, C. H.
    Prashanth, C. R.
    Ramachandra, A. C.
    INTERNATIONAL CONFERENCE ON ADVANCES IN INFORMATION COMMUNICATION TECHNOLOGY & COMPUTING, 2016, 2016,
  • [16] A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction
    Lu, Yu-Sian
    Lee, Cheng-Lung
    Chen, Wei-Zen
    IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021), 2021,
  • [17] Dual-loop DPLL gear-shifting algorithm for fast synchronization
    Kim, B
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1997, 44 (07) : 577 - 586
  • [18] Advantages of dual-loop frequency synthesizers for GSM applications
    Aytur, T
    Khoury, J
    ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 17 - 20
  • [19] A 2-V 1.8-GHz fully integrated CMOS dual-loop frequency synthesizer
    Kan, TKK
    Leung, GCT
    Luong, HC
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (08) : 1012 - 1020
  • [20] A Dual-Loop Delay Locked Loop with Multi Digital Delay Lines for GHz DRAMs
    Moon, Jinyeong
    Lee, Hye-young
    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 313 - 316
12345