1.7-W 50-Gbit/s InPHEMT 4:1 multiplexer IC with a multi-phase clock architecture

被引：0
|
作者：
Sano, K [1 ]
Murata, K [1 ]
Sugitani, S [1 ]
Sugahara, H [1 ]
Enoki, T [1 ]
机构：
[1] NTT Corp, NTT Photon Labs, Atsugi, Kanagawa, Japan
来源：
GAAS IC SYMPOSIUM - 24TH ANNUAL, TECHNICAL DIGEST 2002 | 2002年
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D O I：
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Low-power and high-speed operation of a 4:1 multiplexer IC with a multi-phase clock architecture is reported. The architecture features a togggle-type flip-flop (TFF) that generates a four-phase clock, and a series-gated 4:1 selector (SEL). The fabricated IC using InP HEMTs operates at 50 Gbit/s error-free with 1.71-W power consumption and 1-Vpp output amplitude. The power consumption is less than 113 that of a conventional tree-type InP HEMT 4:1 multiplexer IC and is achieved without any reduction of operation speed and output amplitude.
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页码：159 / 162
页数：4
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