Efficient Design Technique for Pulse Swallow Based Fractional-N frequency Divider

A new high speed pulse swallow based fractional-N frequency divider circuit has been proposed for the frequency range of 2.2 GHz to 4.6 GHz. Moreover, unlike the previously published pulse swallow based frequency divider, the proposed architecture does not include any reset or reload signal for the swallow counter which is basically triggered by the SR latch circuit. Absence of any frequency dependent delay block or any frequency dependant RC delay network to eliminate the conventional frequency divider problems. The proposed architecture has been implemented in 0.18 mu m CMOS and the divider phase-noise at 1 MHz offset frequency is -169.2 dBc/Hz for a carrier signal of 4.6 GHz and the power dissipation from a 1.8 V supply is 13 mW. The proposed frequency divider's swallow counter has no zero division for any counting state which also leads to a higher speed of operation, that has been checked in transistors level simulation. The appropriate figure of merit (FoM) of this divider is 168.40 dB.