A CMOS high-speed pulse swallow frequency divider for ΔΣ fractional-N PLL's

A high-speed pulse-swallow frequency divider suitable for Delta Sigma fractional-N synthesizers is proposed. The proposed structure employs the retiming scheme for the modulus control signal to extend the timing margin, thus remarkably increasing the maximum operating speed. Moreover, unlike the conventional structure, the modulus control signal is set and reset by a single triggering signal to eliminate the unwanted offset at the total division ratio. It simplifies the interface logic between the divider and the Delta Sigma modulator in Delta Sigma fractional-N PLL's. Simulation results show that the proposed divider provides over three times faster operating speed than the conventional one. The proposed divider has been successfully verified in CMOS RF Delta Sigma fractional-N frequency synthesizers.