Modeling of flip-chip underfill delamination and cracking with five input manufacturing variables

The chip corner geometry and the mismatch of the coefficient of thermal expansion cause a local stress concentration in the underfill near the chip corner area. Delamination at the chip-underfill interface and cracks in the underfill often originate from the chip corner and might develop throughout the assembly. This paper presents a modeling approach that allows the estimation of the initial moment of delamination, the growth of delamination and the cracking profiles in flip-chip packages. The reliability model in this work includes five input variables: kerf width, dicing type, laser outrigger presence, sealband material and sealband shape. Thirteen test cells of flip-chip experimental samples were first prepared according to these input variables and were subjected to deep thermal cycling (DTC). C-mode scanning acoustic microscopy (C-SAM), infrared microscopy (IR) and cross-sectioning were used to estimate the underfill failure moments, delamination areas and crack profiles as a reference for subsequent numerical modeling. An artificial neural network (ANN) model was trained to estimate the number of cycles to delamination for cells in the test dataset. The predicted numbers of cycles for all 6 cells in the test dataset were consistent with experimental observations. A finite element model was built to describe the growth of delamination. When the model reached the same delamination area as measured by C-SAM, the difference between the predicted number of cycles and the C-SAM inspection moment were smaller than the inspection interval (250 cycles) for 5 out of 6 cells in validation; the delamination growth model was thus consistent with the experimental observations. The extended finite element method (XFEM) was used to model the underfill cracks without predefined paths. One of the cracks propagated along the diagonal direction, and the other two cracks were along the edges of the die. The directions of edge cracks were in good agreement with the experimental observations, with an error of less than 2.5 degrees for the edge cracks. Overall, with five input manufacturing variables, this modeling approach is able to provide reasonable predictions of the number of cycles to chip-underfill delamination initiation, area of delamination and underfill crack paths in flip-chip packages.