VLSI implementation of area-efficient List Sphere Decoder

Generating soft information in List Sphere Decoder (LSD) increases the computational complexity to select a specific number of candidate lattice points. Among the techniques to reduce the computational complexity, we find that real-valued operation is able to reduce the per-node complexity, ordering process, and storage elements significantly with some tradeoff in speed degradation compared to complex-valued operation. This is useful in systems using large number of antennas and high-order modulation. This paper presents a real-valued LSD architecture for a mode of 4x4 64QAM and compares the hardware complexity of the proposed architecture to that of complex-valued LSD. Although the processing cycle of the proposed architecture is twice that of complex-valued LSD, the hardware complexity of the proposed architecture is less than a fourth of that of the complex-valued LSD. The proposed architecture is also implemented using 0.25um technology and attains an average throughput of 430kvectors/sec at a signal-to-noise ratio (SNR) of 20dB.