Architecture exploration and tools for pipelined coarse-grained reconfigurable arrays

We present a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools perform a simultaneous mapping and pipelining-aware placement, which is then followed by a congestion-avoiding router. Initial experiments show that this flow can succeed in implementing applications with smaller track count and reduced connectivity than existing commercial tools, suggesting changes to the original array architecture. The placer can reduce pipeline latency mismatches on converging paths, simplifying the problem for a pipelining-aware routing step.