Concurrent bit-plane coding architecture for EBCOT in JPEG2000

被引:0
|
作者
Chiang, Jen-Shiun [1 ]
Hsieh, Chang-Yo [1 ]
Liu, Jin-Chan [1 ]
Chien, Cheng-Chih [1 ]
机构
[1] Tamkang Univ, VLSI Lab, Dept Elect Engn, Taipei, Taiwan
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This work presents a concurrent bit-plane coding architecture for EBCOT of JPEG2000. The architecture uses two bit-planes at the same time to encode data and this scheme can reduce the requirement of internal memory efficiently. Compared with the conventional approach, our concurrent architecture can save 8K-bit internal memory. In our proposed architecture, it can process data as long as the data of the two bit-planes are available, and at the same time the system can keep reading data from the external memory. This approach can increase the computation efficiency and avoid the waiting time for reading external data. It can also reduce the access times of the internal memory. Compared with the conventional context modeling architecture, the proposed concurrent bitplane coding architecture can reduce the computation time by more than 50%.
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收藏
页码:4595 / +
页数:2
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