Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design

被引：0
|
作者：
Lu, Chao-Hung [1 ]
Chen, Hung-Ming [2 ]
Liu, Chien-Nan Jimmy [1 ]
Shih, Wen-Yu [1 ]
机构：
[1] Natl Cent Univ, Dept Elect Engn, Tao Yuan, Taiwan
[2] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30050, Taiwan
来源：
DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3 | 2009年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations affect the performance of the chip and the package significantly. In this paper, we have. developed techniques in chip-package codesign to decide the locations of fingers/pads for package routability and signal integrity concerns in chip core design. Our finger/pad assignment is a two-step method: first we optimize the wire congestion problem in package routing, and then we try to minimize the IR-drop violation with finger/pad solution refinement The experimental results are encouraging. Compared with the randomly optimized methods, our approaches reduce in average 42% and 68% of the maximum density in package and 10.61% of IR-drop for test circuits.
引用
收藏
页码：845 / +
页数：2
相关论文
共 50 条
  • [1] Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs
    Lu, Chao-Hung
    Chen, Hung-Ming
    Liu, Chien-Nan Jimmy
    Shih, Wen-Yu
    INTEGRATION-THE VLSI JOURNAL, 2013, 46 (03) : 280 - 289
  • [2] Routability-Driven Bump Assignment for Chip-Package Co-Design
    Chen, Meng-Ling
    Tsai, Tu-Hsiung
    Chen, Hung-Ming
    Chen, Shi-Hao
    2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2014, : 519 - 524
  • [3] System Aware Floorplanning for Chip-Package Co-design
    Pan, Tse-Han
    Franzon, Paul D.
    Srinivas, Vaishnav
    Nagarajan, Mahalingam
    Popovic, Darko
    2023 IEEE 32ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, EPEPS, 2023,
  • [4] Chip-package co-design of a 4.7 GHz VCO
    Donnay, S
    Vaesen, K
    Pieters, P
    Diels, W
    Wambacq, P
    de Raedt, W
    Beyne, E
    Engels, M
    ICM'99: ELEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, 1999, : 145 - 148
  • [5] Chip-package co-design of a 4.7 GHz VCO
    Vaesen, K
    Donnay, S
    Pieters, P
    Carchon, G
    Diels, W
    Wambacq, P
    De Raedt, W
    Beyne, E
    Engels, M
    Bolsens, I
    2000 HD INTERNATIONAL CONFERENCE ON HIGH-DENSITY INTERCONNECT AND SYSTEMS PACKAGING, 2000, 4217 : 301 - 306
  • [6] Analysis of VCO jitter in chip-package co-design
    Parthasarathy, H
    Nayak, G
    Mukund, PR
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS, 2002, : 181 - 184
  • [7] Chip-package co-design of power distribution network for system-in-package applications
    Kim, GW
    Kam, DG
    Chung, DH
    Kim, JH
    6TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, PROCEEDINGS (EPTC 2004), 2004, : 499 - 501
  • [8] Upper/Lower boundary estimation of package interconnect parasitics for chip-package co-design
    Song, Eunseok
    Lee, Heeseok
    Leet, Jungtae
    Jin, Woojin
    Choi, Kiwon
    Yang, Sa-Yoon
    ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2007, : 573 - +
  • [9] CHIP-PACKAGE CO-DESIGN: EFFECT OF SUBSTRATE WARPAGE ON BEOL RELIABILITY
    Raghavan, Sathyanarayanan
    Schmadlak, Ilko
    Leal, George
    Sitaraman, Suresh
    PROCEEDINGS OF THE ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION, 2013, VOL 10, 2014,
  • [10] Chip-package co-design for high performance and reliability off-chip communications
    Shen, M
    Liu, J
    Zheng, LR
    Tenhunen, H
    PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04), 2004, : 31 - 36
12345