A prototype of pixel readout ASIC in 65nm CMOS technology for extreme hit rate detectors at HL-LHC

被引：7

作者：

Paterno, A. ^{[2
,3
]}

Pacher, L. ^{[1
,2
]}

Monteil, E. ^{[1
,2
]}

Loddo, F. ^{[4
]}

Demaria, N. ^{[2
]}

Gaioni, L. ^{[5
,6
]}

De Canio, F. ^{[5
,7
]}

Traversi, G. ^{[5
,6
]}

Re, V. ^{[5
,6
]}

Ratti, L. ^{[5
,7
]}

Rivetti, A. ^{[2
]}

Rolo, M. Da Rocha ^{[2
]}

Dellacasa, G. ^{[2
]}

Mazza, G. ^{[2
]}

Marzocca, C. ^{[4
,8
]}

Licciulli, F. ^{[4
]}

Ciciriello, F. ^{[4
,8
]}

Marconi, S. ^{[9
,10
,15
]}

Placidi, P. ^{[9
,10
]}

Magazzu, G. ^{[11
]}

Stabile, A. ^{[12
]}

Mattiazzo, S. ^{[13
]}

Veri, C. ^{[14
]}

机构：

[1] Univ Turin, Dipartimento Fis, Via Pietro Giuria 1, Turin, Italy

[2] Ist Nazl Fis Nucl, Sez Torino, Via Pietro Giuria 1, Turin, Italy

[3] Politecn Torino, Dipartimento Elettron & Telecomunicaz, Turin, Italy

[4] Ist Nazl Fis Nucl, Sez Bari, Via Orabona 4, Bari, Italy

[5] Ist Nazl Fis Nucl, Sez Pavia, Via Agostino Bassi 6, Pavia, Italy

[6] Univ Bergamo, Dipartimento Ingn & Sci Applicate, Viale Marconi 5, Dalmine, BG, Italy

[7] Univ Pavia, Dipartimento Ingn Ind & Informaz, Pavia, Italy

[8] Politecn Bari, Dipartimento Ingn Elettr & Informaz, Via Orabona 4, Bari, Italy

[9] Ist Nazl Fis Nucl, Sez Perugia, Via Alessandro Pascoli, Perugia, Italy

[10] Univ Perugia, Dipartimento Ingn, Via G Duranti 93, Perugia, Italy

[11] Ist Nazl Fis Nucl, Sez Pisa, Largo Bruno Pontecorvo 3, Pisa, Italy

[12] Ist Nazl Fis Nucl, Sez Milano, Via Celoria 16, Milan, Italy

[13] Univ Padua, Dipartimento Ingn Informaz, Via Gradenigo 6B, Padua, Italy

[14] Univ Salento, Dipartimento Ingn Informaz, Via Monteroni, Lecce, Italy

[15] CERN, CH-1211 Geneva 23, Switzerland

来源：

JOURNAL OF INSTRUMENTATION | 2017年 / 12卷

关键词：

Front-end electronics for detector readout; Particle tracking detectors (Solid-state detectors); Radiation-hard electronics;

D O I：

10.1088/1748-0221/12/02/C02043

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC. A 64 x 64 matrix of 50 x 50 mu m(2) pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm(2) pixel rate, trigger frequency of 1MHz and 12.5 mu sec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

引用

页数：11

共 38 条

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